DocumentCode :
1602715
Title :
Buffered interconnect tree optimization using Lagrangian relaxation and dynamic programming
Author :
Lai, Shih-Yih ; Baldick, Ross
Author_Institution :
Avant! Corp., CA, USA
fYear :
2001
fDate :
6/23/1905 12:00:00 AM
Firstpage :
199
Lastpage :
206
Abstract :
This paper presents a new synthesis method, based on combining bottom-up dynamic programming and Lagrangian relaxation, for finding effective solutions to a delay-constrained buffered interconnect tree. By introducing redundant length constraints and relaxing them using Lagrangian relaxation, our approach decomposes the original problem into a series of dynamic programming sub-problems to synthesize the buffered interconnect tree. We then use an iterative strategy to minimize the interconnect cost and also to satisfy timing and length constraints
Keywords :
dynamic programming; integrated circuit design; integrated circuit interconnections; relaxation theory; trees (mathematics); Lagrangian relaxation; buffered interconnect tree; constant load synthesis; dynamic programming; optimization; Costs; Delay effects; Delay estimation; Dynamic programming; Geometry; Lagrangian functions; Power system interconnection; Routing; Timing; Wire;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Computer Design, 2001. ICCD 2001. Proceedings. 2001 International Conference on
Conference_Location :
Austin, TX
ISSN :
1063-6404
Print_ISBN :
0-7695-1200-3
Type :
conf
DOI :
10.1109/ICCD.2001.955025
Filename :
955025
Link To Document :
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