Title :
Statistical link analysis and in-situ characterization of high-speed memory bus in 3D package systems
Author :
Oh, D. ; Chang, S. ; Jihong Ren ; Ling Yang ; Hai Lan ; Madden, C. ; Schmitt, R.
Author_Institution :
Rambus Inc., Sunnyvale, CA, USA
Abstract :
High-speed link design in a 3D package system poses unique challenges due to the fact that it provides limited visibility to signal quality and that supply noise induced jitter is large due to a poor power distribution network in a small form factor. This paper outlines a statistical link simulation flow to accurately capture the impact of timing jitter due to power supply noise in 3D systems. The analysis includes on-chip jitter accumulation and link-level jitter tracking by considering both passive channel and on-chip signal path. On-chip measurement techniques which allow in-situ testing of the overall link margin are also described.
Keywords :
high-speed integrated circuits; statistical analysis; system-in-package; three-dimensional integrated circuits; timing jitter; 3D package systems; form factor; high-speed link design; high-speed memory bus; in-situ characterization; link-level jitter tracking; on-chip jitter accumulation; on-chip measurement techniques; on-chip signal path; passive channel; power distribution network; power supply noise; signal quality; statistical link analysis; statistical link simulation flow; supply noise induced jitter; timing jitter; Clocks; Jitter; Noise; Power supplies; Random access memory; System-on-a-chip; Three dimensional displays;
Conference_Titel :
Electromagnetic Compatibility (EMC), 2011 IEEE International Symposium on
Conference_Location :
Long Beach, CA, USA
Print_ISBN :
978-1-4577-0812-1
DOI :
10.1109/ISEMC.2011.6038417
