Title :
Full link impedance optimization for serial IOs
Author :
Chunfei Ye ; Xiaoning Ye ; Vargas, E.J. ; Argueta, O.
Author_Institution :
Enterprise Platform Signal Integrity, Intel Corp., Dupont, WA, USA
Abstract :
In this paper, optimal impedance for interconnects, transmitter and receiver design is studied to improve link performance for high-speed differential signaling. Impedance lower than 100Ω for interconnect is shown to improve performance, even when other components such as transmitter, receiver, connector, cable, etc, are designed to 100Ω. Link performance can be further improved if transmitter and receiver can be tuned to impedance targets other than 100Ω. This study is supported by simulation and measurement of 6Gbps serial links, and by simulation of 12Gbps serial links.
Keywords :
electric impedance; impedance matching; interconnections; radio receivers; radio transmitters; signal processing; full link impedance optimization; high speed differential signaling; impedance targets; interconnects; receiver; serial IO; serial links; transmitter; Connectors; Impedance; Integrated circuit interconnections; Receivers; Routing; Topology; Vehicles;
Conference_Titel :
Electromagnetic Compatibility (EMC), 2011 IEEE International Symposium on
Conference_Location :
Long Beach, CA, USA
Print_ISBN :
978-1-4577-0812-1
DOI :
10.1109/ISEMC.2011.6038418
