On-line integrity monitoring of microprocessor control logic

Traditionally, the random logic of most microprocessors is not checked for soft errors due to the great overhead, while regularly-structured memory arrays are often protected with error-correcting codes. This paper presents a low-cost reliability enhancement scheme for the processor´s control logic. We classify control logic signals into static and dynamic control, depending on their changeability for a given instruction, and we employ different mechanisms for each. For static control, the signals used in each pipeline stage are integrated into a signature and verified with a cached check code at commit time; the concept of caching signatures is introduced. Dynamic control is examined on-the-spot; the signals are created using component-level duplication. Fault injection simulations on the RTL model of a MIPS-like processor demonstrate that our scheme can achieve more than 99% coverage on average, with a very small addition of hardware. We have also investigated the criticality of errors in the processor logic, which provides direction for devising an efficient allocation of redundancy