• DocumentCode
    1603180
  • Title

    A timing-driven macro-cell placement algorithm

  • Author

    Mo, Fan ; Tabbara, Abdallah ; Brayton, Robert K.

  • Author_Institution
    California Univ., Berkeley, CA, USA
  • fYear
    2001
  • fDate
    6/23/1905 12:00:00 AM
  • Firstpage
    322
  • Lastpage
    327
  • Abstract
    The timing-driven macro-cell placement algorithm described is based on the force-directed technique. The proposed star net model enables more accurate timing analysis, hence path delay constraints can be handled. In addition, the placer provides functions such as determination of cell orientation, routing estimation and pad placement. The algorithm is iterative and incremental, allowing flexibility in the physical design flow. The placer competes with commercial physical design tools and gives better results in terms of path delay
  • Keywords
    VLSI; circuit layout CAD; integrated circuit layout; iterative methods; optimisation; VLSI design; circuit layout CAD; iterative method; macro-cell placement algorithm; optimisation; path-delay; star net model; timing analysis; Algorithm design and analysis; Delay effects; Engines; Iterative algorithms; Partitioning algorithms; Routing; Timing; Very large scale integration; Wire; Wiring;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Computer Design, 2001. ICCD 2001. Proceedings. 2001 International Conference on
  • Conference_Location
    Austin, TX
  • ISSN
    1063-6404
  • Print_ISBN
    0-7695-1200-3
  • Type

    conf

  • DOI
    10.1109/ICCD.2001.955046
  • Filename
    955046