Bit-serial arithmetic: A novel approach to fuzzy hardware implementation

We propose a novel method of implementing fuzzy logic operations in digital hardware using bit-serial arithmetic. In this approach, signals in a fuzzy system are represented as bit-serial vectors, and manipulated using bit-serial techniques. The advantages of the bit-serial representation are a very simple implementation of min and max operations, and the ability to control the precision of a computation in time, rather than in silicon area. We present a prototype architecture for a fuzzy controller utilizing bit-serial computations, which is implemented in an FPGA. On a Altera Stratix II EP1S80B956C6 FPGA we achieve a throughput of 5.265 million inferences per second, at a clock rate of 94.77 MHz. LUT utilization is approximately 1% of the FPGA device.