Frequency instabilities in phase-locked synthesizers induced by time delays

The influence of time delays on the dynamical behavior of phase-locked synthesizers is reported. Experiments are performed where analog and/or numerical delay lines are introduced in a phase-locked loop (PLL), the main building block of such devices. It is shown that even a first order PLL can exhibit a variety of instabilities leading to chaotic behavior. These instabilities, which can lead to a loss of synchronization of the loop, are the origin of phase and frequency instabilities. An analysis is performed to compare the experimental results with the theory