DocumentCode :
1603444
Title :
A cellular nonlinear network for digital error correction
Author :
Kananen, Asko ; Paasio, Ari ; Lindfors, Saska ; Halonen, Kara
Author_Institution :
Electron. Circuit Design Lab., Helsinki Univ. of Technol., Espoo, Finland
Volume :
3
fYear :
1998
Firstpage :
255
Abstract :
A new concept for correcting errors in digital code is presented. For this purpose a programmable cellular nonlinear network can be used. To achieve high operation speed the high gain output nonlinearity is used. Positive range nonlinearity is combined to the high gain in order to achieve robust operation. The programmability of the network is reduced to only those coefficients actually needed in the processing to further increase the processing speed. An example of this coding scheme is given where the “bubbles” present at the thermometer code generated by a fast flash AID-converter are removed. For this correction operation simulations are given
Keywords :
CMOS integrated circuits; analogue-digital conversion; cellular arrays; digital simulation; error correction; neural nets; nonlinear network synthesis; programmable logic arrays; cellular nonlinear network; coding scheme; correction operation simulation; digital code; digital error correction; fast flash AID-converter; high gain output nonlinearity; high operation speed; positive range nonlinearity; programmability; thermometer code; Cellular networks; Cellular neural networks; Circuit simulation; Decoding; Electronic circuits; Error correction; Laboratories; Latches; Paper technology; Read only memory;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Circuits and Systems, 1998. ISCAS '98. Proceedings of the 1998 IEEE International Symposium on
Conference_Location :
Monterey, CA
Print_ISBN :
0-7803-4455-3
Type :
conf
DOI :
10.1109/ISCAS.1998.703999
Filename :
703999
Link To Document :
بازگشت