Addressing the layout constraint problem when cascading logic gates in nanomagnetic logic

Nanomagnetic Logic (NML) uses ferromagnetic and anti-ferromagnetic coupling to propagate information and to compute logic. In this paper we have addressed a layout constraint problem that surfaces in NML due to magnetic coupling based logic computation. The layout constraint problem poses a severe challenge to designing high density low power cascaded logic. After defining the problem and explaining its cause and impact on NML designs, we have proposed a novel solution to the problem. This helps to design high density and low power cascaded NML circuits.