A static power reduction technique for ternary content addressable memories

Ternary content addressable memories (TCAMs) are attractive for high-speed packet forwarding and classification in network switches and routers. Traditionally, the static power in TCAMs has been a small fraction of the total power due to high activity of TCAMs. However, technology scaling and architecture level techniques are reducing the dynamic power of TCAMs. The technology scaling is also increasing the off-current of transistors. Hence, the static power is becoming a significant portion of the total power consumption in TCAMs. This paper presents a technique to reduce the static power in SRAM-based TCAMs without affecting the speed of operation. We analyze the circuits and present the trade-offs of using this power reduction technique. The simulation results show a significant reduction in the static-power (up to a factor of 11) for an SRAM-based TCAM in 0.13 μm technology.