• DocumentCode
    1603984
  • Title

    AXI Compliant DDR3 Controller

  • Author

    Lakhmani, Vikky ; Ali, Nusrat ; Tripathi, Vijay Shankar

  • Author_Institution
    Dept. of Electr. & Electron. Eng., Uttar Pradesh Tech. Univ., Lucknow, India
  • Volume
    4
  • fYear
    2010
  • Firstpage
    391
  • Lastpage
    395
  • Abstract
    This paper describes the implementation of AXI compliant DDR3 memory controller. It discusses the overall architecture of the DDR3 controller along with the detailed design and operation of its individual sub blocks, the pipelining implemented in the design to increase the design throughput. It also discusses the advantage of DDR3 memories over DDR2 memories and the AXI protocol operation.
  • Keywords
    controllers; memory protocols; pipeline processing; AXI protocol operation; DDR3 memory controller; pipelining implementation; Access protocols; Centralized control; Communication system control; Communication system operations and management; Energy management; Logic; Memory management; Read-write memory; Technology management; Throughput; AXI Interface; AXI access Manager; AXI protocol operation; DDR2 memories; DDR3 memory;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Computer Modeling and Simulation, 2010. ICCMS '10. Second International Conference on
  • Conference_Location
    Sanya, Hainan
  • Print_ISBN
    978-1-4244-5642-0
  • Electronic_ISBN
    978-1-4244-5643-7
  • Type

    conf

  • DOI
    10.1109/ICCMS.2010.291
  • Filename
    5421565
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1603984