A low-jitter clock and data recovery for GDDR5 interface trainings

In this paper, a clock and data recovery (CDR) based on digital phase interpolators using proportional-integral controller, PI² CDR, is proposed for GDDR5 interface trainings, i.e. read training and write training. The proposed CDR is composed of a deserializer, a phase detector, a programmable accumulator, a proportional-integral (PI) controller and four digital phase interpolators instead of two for the purpose of glitch free. Issues such as glitches during the phase switching and phase variation caused by different loads are discussed. Simulation results show that the proposed PI² CDR provides trade-off between low CDR jitter and low power consumption compared to modified and adaptive CDRs.