Optimization of interconnect architectures through coding: A review

Interconnects are becoming a major bottleneck in the design of modern Systems-on-Chip. Power consumption, propagation delay, statistical variability, and reliability are some of the key challenges that must be addressed to fully optimize the interconnect architecture. This work provides a thorough review and analysis of the advantages and possibilities of coding for addressing the aforementioned challenges during the optimization of the communication architecture of a System-on-Chip. An outlook into future research directions is also presented.