Title :
A 622 Mb/s 32×32 scalable shared buffer ATM switch with searchable address queue
Author :
Saito, H. ; Kondoh, H. ; Yamanaka, H. ; Sasaki, Y. ; Tsuzuki, M. ; Kohama, S. ; Yamada, H. ; Matsuda, Y. ; Oshima, K.
Author_Institution :
Inf. Technol. R&D Center, Mitsubishi Electr. Corp., Kanagawa, Japan
Abstract :
The advanced 0.5-μm CMOS technology makes it possible to integrate a huge amount of memories and enables us to apply sophisticated architecture. The implementation of the ATM switch chipset, using new architectures named funnel-structured expandable architecture and the searchable address queueing scheme, is described. A 622 Mb/s 32×8 element switch consists of one buffer LSI and one control LSI. A 622 Mb/s 32×32 switch which comprises four element switches can be installed in one board. The switch has delay-priority control, cell-loss priority control, multicasting function and hierarchical queueing function to accommodate 156 Mb/s, 622 Mb/s and 2.4 Gb/s interfaces
Keywords :
CMOS memory circuits; asynchronous transfer mode; buffer storage; electronic switching systems; large scale integration; queueing theory; telecommunication channels; telecommunication congestion control; 0.5 micron; 156 Mbit/s; 2.4 Gbit/s; 622 Mbit/s; ATM switch chipset; CMOS technology; buffer LSI; cell-loss priority control; control LSI; delay-priority control; funnel-structured expandable architecture; hierarchical queueing function; multicasting function; scalable shared buffer ATM switch; searchable address queue; switch architecture; Asynchronous transfer mode; CMOS technology; Communication equipment; Communication switching; Electronic mail; Information technology; Laboratories; Large scale integration; Research and development; Switches;
Conference_Titel :
Global Telecommunications Conference, 1996. GLOBECOM '96. 'Communications: The Key to Global Prosperity
Conference_Location :
London
Print_ISBN :
0-7803-3336-5
DOI :
10.1109/GLOCOM.1996.587669
