An improved FPGA implementation of a hyperelliptic cryptosystem coprocessor

A mechanism for security that is becoming more popular is the hyperelliptic curve cryptosystem (HECC). HECC derives its security on the difficulties in solving the discrete logarithm problem, where its major advantage is that it offers much shorter key lengths for the same level of security as RSA and ECC. This paper outlines an FPGA implementation of a HECC coprocessor and introduces an efficient FPGA implementation of a finite field multiplier and polynomial addition module used in a HECC. The HECC implementation is based on Cantor´s algorithm for performing point addition and point doubling, which depends on the implementation of efficient polynomial arithmetic blocks that in turn depends on efficient finite field arithmetic blocks. The suggested field multiplication block is one of the most important blocks and is efficient in area, speed, and number of clock cycles to complete the operation.