DocumentCode
1604491
Title
Model for a CMOS Bit-Level Product Cell
Author
González-Navarro, Yesenia E. ; Gomez-Castaneda, F. ; Moreno-Cadenas, José A. ; Flores-Nava, Luis M. ; Arellano-Cárdenas, Oliverio
Author_Institution
CINVESTAV-IPN, Mexico City
fYear
2007
Firstpage
385
Lastpage
388
Abstract
An analysis method for a bit-level product cell used for vector-matrix multiplications is presented. The cell is a combination of a charge injection binary multiplier and an analog accumulator. CID/CCD principles help to understand the cell function and MOS structure equations are used to describe the cell operations.
Keywords
CMOS integrated circuits; matrix algebra; multiplying circuits; CMOS bit-level product cell; MOS structure equations; analog accumulator; charge injection binary multiplier; vector-matrix multiplications; Charge coupled devices; Computer architecture; Encoding; Equations; Neural networks; Semiconductor device modeling; Solid modeling; Solid state circuits; Support vector machines; Very large scale integration; CCD; CID; CMOS; MOS; product cell; vector-matrix multiplication (VMM);
fLanguage
English
Publisher
ieee
Conference_Titel
Electrical and Electronics Engineering, 2007. ICEEE 2007. 4th International Conference on
Conference_Location
Mexico City
Print_ISBN
978-1-4244-1166-5
Electronic_ISBN
978-1-4244-1166-5
Type
conf
DOI
10.1109/ICEEE.2007.4345046
Filename
4345046
Link To Document