Title :
32% Slew rate and 27% data rate improved 2×VDD output buffer using PVTL compensation
Author :
Tzung-Je Lee ; Kai-Wei Ruan ; Chua-Chin Wang
Author_Institution :
Dept. of Comput. Sci. & Inf. Eng., Cheng Shiu Univ., Kaohsiung, Taiwan
Abstract :
A 2×VDD Output Buffer using PVTL compensation is proposed in this paper. Beside the PVT compensation, a Leakage compensation circuit is employed. With the proposed Leakage compensation circuit, the SR (slew rate) and data rate are improved by 32% and 27%, respectively, for VDDIO = 1.8 V at the worst case. Moreover, the reliability problem caused by the unstable voltage, gate oxide overstress and hot carrier degradation is avoided. The proposed design is implemented using a typical 90 nm CMOS process. The core area is 0.425 mm × 0.0563 mm. The SR is simulated to be 1.3-3.0 V/ns. The data rate is simulated to be 454, 370, and 500 MHz for VDDIO = 1.8, 1.2, and 1.0 V, respectively.
Keywords :
CMOS integrated circuits; buffer circuits; compensation; detector circuits; hot carriers; integrated circuit design; integrated circuit reliability; leakage currents; 2×VDD output buffer; CMOS process; PVTL compensation; SR; data rate; frequency 370 MHz; frequency 454 MHz; frequency 500 MHz; gate oxide overstress; hot carrier degradation; leakage compensation circuit; process compensation; reliability problem; size 0.0563 mm; size 0.425 mm; size 90 nm; slew rate; temperature compensation; voltage 1.0 V; voltage 1.2 V; voltage 1.8 V; voltage compensation; CMOS process; Detectors; Generators; Image edge detection; Leakage currents; Logic gates; Partial discharges; leakage compensation; mixed-voltage; nano scale; output buffer; slew rate;
Conference_Titel :
IC Design & Technology (ICICDT), 2014 IEEE International Conference on
Conference_Location :
Austin, TX
DOI :
10.1109/ICICDT.2014.6838601
