Title :
Modeling the interconnects of Xilinx Virtex FPGAs and derivation of their test configurations
Author :
Giasson, Christian ; Sun, Xiaoling
Author_Institution :
Dept. of Electr. & Comput. Eng., Alberta Univ., Edmonton, Alta., Canada
Abstract :
The paper employs bipartite graphs to model the local interconnect resources of Xilinx Virtex field programmable gate arrays (FPGAs). A computer algorithm is introduced to derive a minimal or near minimal set of test configurations (TCs) by solving edge coloring problems of the graphs, where each color represents a TC. A minimal set of 26 TCs was obtained for Virtex FPGAs.
Keywords :
circuit layout CAD; field programmable gate arrays; graph colouring; integrated circuit interconnections; integrated circuit layout; network routing; Xilinx Virtex FPGA interconnects; bipartite graphs; computer algorithm; edge coloring problems; field programmable gate arrays; interconnect modeling; routing path; test configurations; Bipartite graph; Field programmable gate arrays; Programmable logic arrays; Programmable logic devices; Routing; Sun; Switches; Testing; Tiles; Wire;
Conference_Titel :
Electrical and Computer Engineering, 2004. Canadian Conference on
Print_ISBN :
0-7803-8253-6
DOI :
10.1109/CCECE.2004.1345243
