A dual round-robin arbiter for split-transaction buses in system-on-chip implementations

This paper presents a dual round-robin arbiter for split transaction buses with separate address and data lines for use in system-on-chip implementations of shared-memory multiprocessors. The dual round-robin arbiter provides independent arbitration for requests on the address bus and responses on the data bus. For writeback requests that require simultaneous use of address and data lines, the arbiters for the separate buses interact in order to allow a writeback to proceed. The arbiters serve other requests until such time that they can match their separate states to serve a writeback request. It can be shown that this approach ensures a bounded waiting time and avoids the use of ad hoc approaches to temporarily increase request priority. A VHDL implementation of the arbiter design has been completed and tested in detailed logic simulation to confirm proper functionality in preparation for integration with other components in programmable logic.