• DocumentCode
    1605510
  • Title

    A gray-based block-matching algorithm and its VLSI architecture

  • Author

    Shiau, Yeu-Horng ; Chen, Pei-Yin ; Jou, Jer Min

  • Author_Institution
    Dept. of Electr. Eng., Nat. Cheng Kung Univ., Tainan, Taiwan
  • fYear
    1999
  • fDate
    6/21/1905 12:00:00 AM
  • Firstpage
    54
  • Lastpage
    63
  • Abstract
    In this paper, we propose an efficient gray-based block-matching algorithm (GBMA) and its VLSI architecture. Based on the gray system theory, the GBMA can determine the better motion vectors of image blocks quickly. The experimental results show that the proposed algorithm performs better than other search algorithms, such as TSS, CS, PHODS, FSS, and SES, in terms of four different measures: 1) average MSE per pixel, 2) average PSNR, 3) average prediction errors per pixel, and 4) average search points per frame. The VLSI architecture of the algorithm has been designed and implemented, and it can yield a search rate of 680 K blocks/sec with a clock rate of 66 MHz
  • Keywords
    VLSI; motion estimation; search problems; VLSI architecture; gray-based block-matching algorithm; image blocks; motion vectors; search algorithms; Algorithm design and analysis; Bit rate; Clocks; Frequency selective surfaces; Image sequences; Motion estimation; PSNR; Performance evaluation; Redundancy; Very large scale integration;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Signal Processing Systems, 1999. SiPS 99. 1999 IEEE Workshop on
  • Conference_Location
    Taipei
  • ISSN
    1520-6130
  • Print_ISBN
    0-7803-5650-0
  • Type

    conf

  • DOI
    10.1109/SIPS.1999.822310
  • Filename
    822310