DocumentCode :
1605625
Title :
VLSI architecture for hierarchical mesh-based motion estimation
Author :
Badawy, Wael ; Zhang, Guoqing ; Bayoumi, Magdy
Author_Institution :
Center for Adv. Comput. Studies, Univ. of Southwestern Louisiana, Lafayette, LA, USA
fYear :
1999
fDate :
6/21/1905 12:00:00 AM
Firstpage :
110
Lastpage :
119
Abstract :
Methods for object-based compression and composition of natural and synthetic video content are currently emerging in standards such as MPEG-4 and VRML. This paper shows a novel VLSI architecture for generating content-based video object representation. The architecture uses a novel technique, borrowed from the 3D modeling, to optimize the mesh coding. The architecture generates the mesh nodes location as well as the associated motion vectors. The performance results show that the prototype contributes practical delay, and it can be used in online application and the power consumption shows that it is good enough in mobile application. Moreover, the number of bits used for the coding shows that the architecture is suitable for very low bit rate applications since it reuses the motion vector values
Keywords :
VLSI; image representation; motion estimation; video coding; VLSI architecture; associated motion vectors; content-based; mesh coding; mesh nodes location; motion estimation; video object representation; Computer architecture; Costs; MPEG 4 Standard; Mesh generation; Motion estimation; Prototypes; Real time systems; Very large scale integration; Video compression; Videoconference;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Signal Processing Systems, 1999. SiPS 99. 1999 IEEE Workshop on
Conference_Location :
Taipei
ISSN :
1520-6130
Print_ISBN :
0-7803-5650-0
Type :
conf
DOI :
10.1109/SIPS.1999.822316
Filename :
822316
Link To Document :
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