A low-power reconfigurable data-flow driven DSP system

Author

Wan, Marlene ; Zhang, Hui ; Benes, Martin ; Rabaey, Jan

Author_Institution

Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA

fYear

1999

fDate

6/21/1905 12:00:00 AM

Firstpage

191

Lastpage

200

Abstract

Reconfigurable architectures have emerged as a promising implementation platform to provide high-flexibility, high-performance, and low-power solutions for future wireless embedded devices. We discuss in details a reconfigurable data-flow driven architecture, including the computation model, communication mechanism, and implementation. We also describe a set of software tools developed to perform automatic mapping from algorithms to the architecture, as well as to evaluate the resulting performance and energy of the mapping. Finally, we present results on digital signal processing and wireless communication algorithms to show the energy efficiency of the system and the effectiveness of the tools. Our system shows more than one order of magnitude of improvement in terms of energy efficiency when compared to low-power programmable processors

Keywords

data flow computing; reconfigurable architectures; signal processing; automatic mapping; communication mechanism; computation model; data-flow driven architecture; reconfigurable architectures; software tools; wireless embedded devices; Computational modeling; Computer architecture; Digital signal processing; Energy efficiency; Performance evaluation; Reconfigurable architectures; Signal processing algorithms; Software algorithms; Software tools; Wireless communication;

fLanguage

English

Publisher

ieee

Conference_Titel

Signal Processing Systems, 1999. SiPS 99. 1999 IEEE Workshop on

Conference_Location

Taipei

ISSN

1520-6130

Print_ISBN

0-7803-5650-0

Type

conf

DOI

10.1109/SIPS.1999.822324

Filename

822324