• DocumentCode
    1605846
  • Title

    Cache-In-Memory

  • Author

    Zawodny, Jason T. ; Kogge, Peter M.

  • Author_Institution
    Dept. of Comput. Sci. & Eng., Notre Dame Univ., IN, USA
  • fYear
    2001
  • fDate
    6/23/1905 12:00:00 AM
  • Firstpage
    3
  • Lastpage
    11
  • Abstract
    The new technology of Processing-In-Memory now allows relatively large DRAM memory macros to be positioned on the same die with processing logic. Despite the high bandwidth and low latency possible with such macros, more of both is always better. Classical techniques such as caching are typically used for such performance gains, but at the cost of high power. The paper summarizes some recent work into the potential of utilizing structures within such memory macros as cache substitutes, and under what conditions power savings may result
  • Keywords
    DRAM chips; cache storage; macros; CIM; Processing-In-Memory; bandwidth; cache substitutes; caching; large DRAM memory macros; low latency; memory macros; performance gains; power savings; processing logic; DRAM chips;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Innovative Architecture for Future Generation High-Performance Processors and Systems, 2001
  • Conference_Location
    Maui, HI
  • ISSN
    1537-3223
  • Print_ISBN
    0-7695-1309-3
  • Type

    conf

  • DOI
    10.1109/IWIA.2001.955191
  • Filename
    955191