Title : 
Cache coherence protocol for home proxy cache on RHiNET and its preliminary performance estimation
         
        
            Author : 
Nakajo, Hironori ; Ishii, Masaaki ; Yamamoto, Junji ; Kudo, Tomohiro ; Yokoyama, Tomonori ; Tsuchiya, Jun-Ichiro ; Amano, Hideharu
         
        
            Author_Institution : 
Dept. of Comput., Inf. & Commun. Sci., Tokyo Univ. of Agric. & Technol., Japan
         
        
        
            fDate : 
6/23/1905 12:00:00 AM
         
        
        
        
            Abstract : 
LASN (Local Area System Network) is a new class of networks which has the advantages of both SANS and LANs. RHiNET (RWCP high performance network) is the first network designed with the concepts of an LASN. A prototype called RHiNET-1 using 1.33 Gbps optical interconnections is available for research on cluster computing. In the case of implementing distributed shared-memory system on a cluster system, software based cache memory is used in order to reduce the number of accesses to shared-memory and a large amount of communication in the network. We have proposed Home Proxy Cache which keeps copies of pages in home memory in order to avoid I/O bus bottleneck when there are many accesses from the other nodes to the home memory. In this paper, a network interface of RHiNET is introduced and the detailed coherence protocol for a distributed shared-memory system is presented. The protocol will be implemented in the RHiNET network interface. We have estimated effectiveness of Home Proxy Cache with RHiNET-1 and RHiNET-2 in cases of Read Miss and Write Miss to Cache Memory
         
        
            Keywords : 
cache storage; local area networks; memory protocols; performance evaluation; workstation clusters; LANs; Local Area System Network; RHiNET; SANs; cache memory; cluster computing; coherence protocol; distributed shared-memory system; home proxy cache; optical interconnections; Cache memories;
         
        
        
        
            Conference_Titel : 
Innovative Architecture for Future Generation High-Performance Processors and Systems, 2001
         
        
            Conference_Location : 
Maui, HI
         
        
        
            Print_ISBN : 
0-7695-1309-3
         
        
        
            DOI : 
10.1109/IWIA.2001.955197