DocumentCode
1606097
Title
Architecture and implementation of a single-chip programmable digital television and media processor
Author
Dutta, Santanu ; Singh, Deepak ; Mehra, Vijay
Author_Institution
Philips Semicond., Sunnyvale, CA, USA
fYear
1999
fDate
6/21/1905 12:00:00 AM
Firstpage
321
Lastpage
330
Abstract
This paper describes the architecture, functionality and design of TM-2700-a digital television and media processor chip from Philips Semiconductors. The chip not only supports all eighteen digital television picture formats prescribed by the United States Advanced Television Systems Committee (ATSC), from standard-definition to wide-angle high-definition video, but has also the power to handle High-Definition Television (HDTV) video and audio source decoding (high-level MPEG-2 video, AC-3 and ProLogic audio, closed captioning, etc.) as well as the flexibility to process advanced interactive services. TM-2700 is a programmable processor with a very powerful, general-purpose Very Long Instruction Word (VLIW) Central Processing Unit (CPU) core that implements many non-trivial multimedia algorithms, coordinates all on-chip activities, and runs a small real-time operating system. Aided by an array of peripheral devices and high-performance buses, the CPU core facilitates concurrent processing of audio, video, graphics, and communication-data
Keywords
digital signal processing chips; digital television; video signal processing; AC-3; MPEG-2 video; Philips Semiconductors; ProLogic audio; TM-2700; closed captioning; digital television and media processor; interactive services; multimedia; Central Processing Unit; Decoding; Digital TV; HDTV; High definition video; Multimedia systems; Operating systems; Real time systems; System-on-a-chip; VLIW;
fLanguage
English
Publisher
ieee
Conference_Titel
Signal Processing Systems, 1999. SiPS 99. 1999 IEEE Workshop on
Conference_Location
Taipei
ISSN
1520-6130
Print_ISBN
0-7803-5650-0
Type
conf
DOI
10.1109/SIPS.1999.822337
Filename
822337
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