Title :
An analysis and design of an optimal programmable analog CMOS synapse
Author :
Narathong, C. ; Staab, J. ; Geiger, S.
Author_Institution :
Dept. of Electr. Eng., Wisconsin Univ., Platteville, WI, USA
Abstract :
Reports on a project to develop an optimally sized programmable analog CMOS synapse cell library which is readily available for the construction of a high-density VLSI neural network. A set of optimal design equations is derived from standard CMOS equations. The derivation of the design equations and the evaluation of the size (silicon area) and performance of the synapse cell are discussed
Keywords :
CMOS integrated circuits; VLSI; analogue processing circuits; neural chips; cell library; high-density VLSI neural network; optimal design equations; optimal programmable analog CMOS synapse; performance; size; Algorithm design and analysis; Circuit testing; Equations; Libraries; Neural networks; Neurons; Power supplies; Silicon; Very large scale integration; Voltage;
Conference_Titel :
ASIC Conference and Exhibit, 1992., Proceedings of Fifth Annual IEEE International
Conference_Location :
Rochester, NY
Print_ISBN :
0-7803-0768-2
DOI :
10.1109/ASIC.1992.270196
