Title :
An analog parallel processor for the dynamic programming paradigm
Author :
Soumyanath, K. ; Arx, Jeffrey Von
Author_Institution :
Dept. of Electr. Eng., Tufts Univ., Medford, MA, USA
Abstract :
A novel analog parallel approach to the implementation of the dynamic programming paradigm is described. The approach has been used to design a test chip which solves the single source, shortest path problem in a fully connected eight-mode network. The distributed processor design has been fabricated in a 2-μm double poly low noise CMOS process using a die area of 2.22×2.22 mils. The design has a typical setting time of 100 ns and a worst case power dissipation of 3.5 W
Keywords :
CMOS integrated circuits; analogue processing circuits; dynamic programming; 100 ns; 2 micron; 3.5 W; analog parallel processor; distributed processor design; double poly low noise CMOS process; dynamic programming paradigm; fully connected eight-mode network; setting time; shortest path problem; test chip; worst case power dissipation; CMOS process; Costs; Dynamic programming; Equations; Parallel processing; Physics; Power dissipation; Process design; Shortest path problem; Testing;
Conference_Titel :
ASIC Conference and Exhibit, 1992., Proceedings of Fifth Annual IEEE International
Conference_Location :
Rochester, NY
Print_ISBN :
0-7803-0768-2
DOI :
10.1109/ASIC.1992.270200
