Title :
The COREWARE methodology: building a 200 MFLOP processor in 9 man months
Author :
Stearns, C. ; Harrington, Tom ; Stenbeck, Ann
Author_Institution :
Vertex Semicond., San Jose, CA, USA
Abstract :
Utilizing the COREWARE methodology, a 163-MFLOP graphics transformation processor is realized in a 0.7-μm two-layer metal CMOS process operating at 40 MHz. The COREWARE methodology allows the processor to be specified, designed, and implemented in nine man months. The graphics processor provides 3.3 million transformed, perspective divided, clip tested 3D vertices per second. The matrix multiplication is based on the interleaved multiplier accumulator algorithm, which transposes the order of the arithmetic operations to accomplish maximum throughput
Keywords :
CMOS integrated circuits; circuit CAD; digital arithmetic; logic CAD; microprocessor chips; 0.7 micron; 200 MFLOPS; 40 MHz; COREWARE methodology; arithmetic operations; clip tested 3D vertices; graphics transformation processor; interleaved multiplier accumulator algorithm; matrix multiplication; two-layer metal CMOS process; Algorithm design and analysis; Arithmetic; CMOS logic circuits; CMOS process; Graphics; Hardware; Large scale integration; Pipelines; Propagation delay; Testing;
Conference_Titel :
ASIC Conference and Exhibit, 1992., Proceedings of Fifth Annual IEEE International
Conference_Location :
Rochester, NY
Print_ISBN :
0-7803-0768-2
DOI :
10.1109/ASIC.1992.270202
