Low-power CDMA multiuser receiver architectures

Author

Long, Tao ; Shanbhag, Naresh R.

Author_Institution

Dept. of Electr. & Comput. Eng., Illinois Univ., Urbana, IL, USA

fYear

1999

fDate

6/21/1905 12:00:00 AM

Firstpage

493

Lastpage

502

Abstract

Presented in this paper are low-power, reconfigurable adaptive CDMA multiuser receiver architectures developed via dynamic algorithmic transforms (DAT). The architectures achieve low-power operation via run-time reconfiguration of receiver complexity to match the requirements of a time-varying multiuser channel. Simulation results with 0.25 μm, 2.3 V CMOS technology parameters indicate that the proposed architectures have high resistance to the near-far problem, and can achieve up to 60.4% in power savings compared to architectures without DAT depending on the interference situation

Keywords

CMOS integrated circuits; code division multiple access; computational complexity; digital simulation; radio access networks; CDMA multiuser receiver architectures; CMOS technology; dynamic algorithmic transforms; receiver complexity; run-time reconfiguration; simulation results; time-varying multiuser channel; CMOS technology; Computer architecture; Detectors; Hardware; Heuristic algorithms; Multiaccess communication; Multimedia systems; Multiple access interference; Multiuser detection; Throughput;

fLanguage

English

Publisher

ieee

Conference_Titel

Signal Processing Systems, 1999. SiPS 99. 1999 IEEE Workshop on

Conference_Location

Taipei

ISSN

1520-6130

Print_ISBN

0-7803-5650-0

Type

conf

DOI

10.1109/SIPS.1999.822355

Filename

822355