DocumentCode
1606493
Title
Behavioural VHDL code generation for synchronous FSMs
Author
Wang, X.J. ; Grainger, S.R.W. ; Cooper, A.
Author_Institution
Sch. of Eng., Staffordshire Univ., Stafford, UK
fYear
1992
Firstpage
529
Lastpage
532
Abstract
An interactive system, HLSS, that generates behavioral VHDL (VHSIC Hardware Description Language) code for synchronous finite state machines (FSMs) is described. A process model graph that separates the combinational and sequential logic elements in a FSM is used in code generation. The generated code can be used for synthesis as well as simulation. A complete example is given
Keywords
digital simulation; finite state machines; logic CAD; specification languages; HLSS; behavioral VHDL; code generation; combinational logic elements; interactive system; process model graph; sequential logic elements; synchronous FSMs; synchronous finite state machines; Clocks; Digital systems; Documentation; Graphics; Hardware design languages; High level synthesis; Interactive systems; Logic; Navigation; Synchronous generators;
fLanguage
English
Publisher
ieee
Conference_Titel
ASIC Conference and Exhibit, 1992., Proceedings of Fifth Annual IEEE International
Conference_Location
Rochester, NY
Print_ISBN
0-7803-0768-2
Type
conf
DOI
10.1109/ASIC.1992.270206
Filename
270206
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