Power efficient photonic networks for many-core architectures

Continuous technology scaling will enable future many-core architectures to interconnect hundreds and even thousands of cores within multi-chip modules. With increasing number of cores, it becomes essential to reduce the hop count while delivering high interconnect bandwidth at low power. In this paper, we propose SPRINT (Scalable Photonic Reconfigurable Interconnect) that can scale to large cores using photonic switching implemented with silicon microring resonators. Micro-ring resonators are low-power, high-bandwidth switching devices that can be arranged to function as a high-radix router with reduced complexity and power. We will first show the design of a 64 core cluster using optical interconnects and electrical packet switching. To build scalable switching crossconnects, we investigate the design of 256, 512 and 1024-socket versions of SPRINT connected using passive arrayed waveguide grating (AWG). Our proposed switching crossconnect minimizes the hop count to four for a 1024 core network while reducing the power dissipation, increasing the bandwidth and reducing the switching complexity.