A new approach for configuration compression in Virtex based RTR systems

Run-time reconfiguration (RTR) is a new high performance computing paradigm that uses reconfigurable architectures (FPGAs) and promises an intermediate trade-off between the flexibility of microprocessors and the performance of ASICs. Unfortunately, the required time to map high computing parts of an application to FPGA is considerable and affects the performance of RTR systems. In order to deal with this problem and increase the computing power of such systems, it is important to develop hardware and software systems to reduce or eliminate reconfiguration delay. We have developed a new approach for reconfiguration overhead reduction in Virtex based RTR systems by configuration compression. We have also introduced an approach based on genetic algorithm to find the best interframe similarities of configuration frames to improve the compression ratio.