Title :
Robin Hood: a system timing verifier for multi-phase level-sensitive clock designs
Author :
Tsay, Ren-Song ; Lin, Ichiang
Author_Institution :
IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA
Abstract :
An efficient system timing verification approach that employs latch graph representation is reported. It is a general approach that can handle most blocking schemes. Both early and late mode timing constraints are considered. The tool generates a detailed stack report to help designers identify where and how much the correction should be in case of violations. The algorithm has been implemented and tested on several real designs. An example with 1926 latches and dense interconnections is verified in 0.62 s
Keywords :
clocks; flip-flops; logic CAD; Robin Hood; blocking schemes; dense interconnections; latch graph representation; multi-phase level-sensitive clock designs; stack report; system timing verifier; timing constraints; Algorithm design and analysis; Clocks; Data processing; Digital systems; Logic; Master-slave; Performance analysis; Product design; Testing; Timing;
Conference_Titel :
ASIC Conference and Exhibit, 1992., Proceedings of Fifth Annual IEEE International
Conference_Location :
Rochester, NY
Print_ISBN :
0-7803-0768-2
DOI :
10.1109/ASIC.1992.270209
