DocumentCode
1606591
Title
A low-voltage metal-programmable SRAM compiler for gate array
Author
Svejda, Frank J. ; Tupuri, Raghuram S. ; Madhuri, Sudha ; Rath, Randy
Author_Institution
Texas Instrum. Inc., Dallas, TX, USA
fYear
1992
Firstpage
513
Lastpage
515
Abstract
A faster and more area efficient metal-programmable SRAM compiler for a 3.3 V 0.65 μm effective CMOS sea-of-gates (SOG) array has been designed. A base cell, optimized for memory, features reduced bit and word-line parasitics in order to improve speed and provide high density SRAMs for ASIC applications
Keywords
CMOS integrated circuits; SRAM chips; application specific integrated circuits; logic arrays; 0.65 micron; 3.3 V; ASIC applications; CMOS sea-of-gates array; gate array; high density SRAMs; metal-programmable SRAM compiler; speed; word-line parasitics; Application specific integrated circuits; Clocks; Costs; Design optimization; Instruments; Latches; Logic arrays; Parasitic capacitance; Personal digital assistants; Random access memory;
fLanguage
English
Publisher
ieee
Conference_Titel
ASIC Conference and Exhibit, 1992., Proceedings of Fifth Annual IEEE International
Conference_Location
Rochester, NY
Print_ISBN
0-7803-0768-2
Type
conf
DOI
10.1109/ASIC.1992.270210
Filename
270210
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