Title :
A high speed metal programmable static RAM compiler for 0.7 μm CMOS gate array
Author :
Honnenhalli, S. ; Shiffer, Jim ; Subramanyam, Shiva ; Eastwick, David ; Kim, Doo Young ; Jiang, Jian
Author_Institution :
Compass Design Autom., San Jose, CA, USA
Abstract :
A static RAM compiler has been developed for a new 0.7 micron Leff CMOS gate array. The compiler is fully metal programmable and can compile RAMs from 8 bits to 64 K bits with typical access times of 4 ns to 10 ns, respectively. It supports partially decoded RAMs and variable aspect ratios. The compiler is well integrated into CAD tools
Keywords :
CMOS integrated circuits; SRAM chips; logic CAD; logic arrays; 0.7 micron; 4 to 10 ns; 8 bit to 64 Kbit; CAD tools; CMOS gate array; access times; metal programmable static RAM compiler; partially decoded RAMs; variable aspect ratios; Clocks; Decoding; Design automation; Pins; Program processors; Random access memory; Read-write memory; Routing; Synchronous generators; Very large scale integration;
Conference_Titel :
ASIC Conference and Exhibit, 1992., Proceedings of Fifth Annual IEEE International
Conference_Location :
Rochester, NY
Print_ISBN :
0-7803-0768-2
DOI :
10.1109/ASIC.1992.270212
