Title :
A parallel BDD engine for logic verification
Author :
Caban, Dariusz ; Milford, David
Author_Institution :
Dept. of Electr. & Electron. Eng., Bristol Univ., UK
Abstract :
The use of binary decision diagrams (BDDs) for logic verification in a multiprocessing environment is described. A BDD engine, implemented as an array of transputers, is used as an accelerator for the NODEN suite of logic verification software. The efficiency of the parallel processing scheme was tested by constructing the BDD representation of a simple arithmetic logic unit (ALU) circuit
Keywords :
logic CAD; parallel algorithms; transputer systems; NODEN suite; accelerator; arithmetic logic unit; binary decision diagrams; logic verification; multiprocessing environment; parallel BDD engine; transputers; Arithmetic; Binary decision diagrams; Boolean functions; Circuit testing; Data structures; Engines; Logic arrays; Logic circuits; Logic testing; Parallel processing;
Conference_Titel :
ASIC Conference and Exhibit, 1992., Proceedings of Fifth Annual IEEE International
Conference_Location :
Rochester, NY
Print_ISBN :
0-7803-0768-2
DOI :
10.1109/ASIC.1992.270213
