Title :
An efficient MOS VLSI timing simulator on parallel computers
Author :
Chung, Steve S. ; Chang, T.-S.
Author_Institution :
Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan
Abstract :
A new timing simulator for MOS VLSI circuits has been developed. It is capable of performing accurate transient analysis, simulating large circuits, and improving the simulation speed. For simulating tightly coupled circuits, floating capacitors are used, and accuracy can be preserved. an efficient subcircuit model with latency exploitation is employed to reduce the simulation time. Benchmark tests on multiprocessors show that the simulation speed is about an order of speed faster than that of single CPUs for a number of circuits
Keywords :
MOS integrated circuits; VLSI; circuit analysis computing; digital simulation; parallel algorithms; transient response; MOS VLSI timing simulator; floating capacitors; latency exploitation; multiprocessors; simulation speed; simulation time; subcircuit model; tightly coupled circuits; transient analysis; Analytical models; Circuit simulation; Circuit testing; Computational modeling; Computer simulation; Concurrent computing; Coupling circuits; Timing; Transient analysis; Very large scale integration;
Conference_Titel :
ASIC Conference and Exhibit, 1992., Proceedings of Fifth Annual IEEE International
Conference_Location :
Rochester, NY
Print_ISBN :
0-7803-0768-2
DOI :
10.1109/ASIC.1992.270214
