Title :
Design of an area efficient Reed-Solomon decoder ASIC chip
Author :
Chang, Hyunman ; Sunwoo, Myung H.
Author_Institution :
Sch. of Electr. & Electron. Eng., Ajou Univ., Suwon, South Korea
fDate :
6/21/1905 12:00:00 AM
Abstract :
We describe an area efficient pipelined Reed-Solomon (RS) decoder. We propose two simple basic cell architectures which evaluate the error locator and the error magnitude polynomial in the general Euclid´s algorithm. The evaluation involves high computational complexity, and thus, it affects the speed and the hardware complexity of RS decoders. The proposed architectures can reduce the hardware complexity by more than 16% of existing RS decoder architectures. The proposed RS decoder can be programmed to decode four RS codes defined in Galois field 28, i.e., (200, 188), (120, 108), (60, 48), and (40, 28) and can correct up to six errors. The fabricated FEC (Forward Error Correction) chip including the RS and Viterbi decoders operates at 40 MHz. The total number of gates for the RS decoder is about 31,000 and the FEC chip contains about 76,000 gates
Keywords :
Galois fields; Reed-Solomon codes; application specific integrated circuits; circuit complexity; decoding; digital signal processing chips; forward error correction; high level synthesis; Galois field; RS decoder; Reed-Solomon decoder ASIC chip; Viterbi decoders; area efficient pipelined Reed-Solomon decoder; basic cell architectures; computational complexity; error locator; error magnitude polynomial; forward error correction chip; gates; Application specific integrated circuits; Computational complexity; Computer architecture; Decoding; Error correction codes; Forward error correction; Galois fields; Hardware; Polynomials; Reed-Solomon codes;
Conference_Titel :
Signal Processing Systems, 1999. SiPS 99. 1999 IEEE Workshop on
Conference_Location :
Taipei
Print_ISBN :
0-7803-5650-0
DOI :
10.1109/SIPS.1999.822364