MATEG: a hierarchical test generator for module-based circuits

Author

Chiang, David R. ; Cutler, Michal

Author_Institution

Dept. of Comput. Sci., State Univ. of New York, Binghamton, NY, USA

fYear

1992

Firstpage

491

Lastpage

494

Abstract

The general algorithms and heuristics developed in the module-level automatic test pattern generator called MATEG are described. MATEG is a generalization of the branch-and-bound test generation algorithm for module-based circuits. MATEG retains accuracy of the deterministic test generation, and reduces computation time by exploiting the hierarchy in the circuit-under-test. Some experimental results are presented to demonstrate the efficiency of this approach

Keywords

automatic testing; integrated circuit testing; logic testing; modules; MATEG; automatic test pattern generator; branch-and-bound test generation algorithm; circuit-under-test; computation time; deterministic test generation; hierarchical test generator; module-based circuits; Automatic testing; Circuit synthesis; Circuit testing; Computer science; Design methodology; Heuristic algorithms; Logic circuits; Logic gates; Logic testing; Test pattern generators;

fLanguage

English

Publisher

ieee

Conference_Titel

ASIC Conference and Exhibit, 1992., Proceedings of Fifth Annual IEEE International

Conference_Location

Rochester, NY

Print_ISBN

0-7803-0768-2

Type

conf

DOI

10.1109/ASIC.1992.270215

Filename

270215

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1606703