Low power 5 GHz voltage-controlled oscillator using negative resistance enhancement technique

In this paper, we present low phase noise and low power of the voltage-controlled oscillators (VCOs) for 5 GHz applications. This chip is implemented by Taiwan Semiconductor Manufacturing Company (TSMC) standard 0.18μm CMOS process. The designed circuit topology is included a modified conventional pmos cross couple configuration. It is adopted pseudo resistance and using negative resistance enhancement technique. At the supply voltage 1v, the measured output phase noise is -120.13 dBc/Hz at 1MHz offset frequency from the carrier frequency of 5.47 GHz. The core power consumption is 2.65 mW, and tuning range of frequency is about 900MHz, from 4.68 to 5.58 GHz. The chip area is 0.754×0.544 (mm²).