Title :
A scalable low-complexity digit-serial VLSI architecture for RSA cryptosystem
Author :
Leu, Jye-Jong ; Wu, An-Yeu
Author_Institution :
Dept. of Electr. Eng., Nat. Central Univ., Chung-Li, Taiwan
fDate :
6/21/1905 12:00:00 AM
Abstract :
The Booth-encoded Montgomery modular multiplication algorithm is proposed to reduce the iteration number to about n/2 in each Montgomery operation. In addition, we apply the folding and unfolding technique to shorten the critical path. Finally, we propose the 2 bit-digit-serial pipelined architecture to process RSA en/decryption in a more efficient way. By applying the proposed algorithm in RSA design, the hardware complexity can be reduced by 15% compared with most RSA VLSI designs using the Montgomery modular multiplication algorithm
Keywords :
VLSI; circuit complexity; digital arithmetic; digital signal processing chips; public key cryptography; Montgomery modular multiplication algorithm; RSA cryptosystem; decryption; digit-serial VLSI architecture; digit-serial pipelined architecture; folding technique; hardware complexity; iteration number; public key cryptography; unfolding technique; Algorithm design and analysis; Computer hacking; Computer networks; Data security; Hardware; Protection; Public key; Public key cryptography; Telephony; Very large scale integration;
Conference_Titel :
Signal Processing Systems, 1999. SiPS 99. 1999 IEEE Workshop on
Conference_Location :
Taipei
Print_ISBN :
0-7803-5650-0
DOI :
10.1109/SIPS.1999.822365
