A power-aware behavioral model of a five-state phase-frequency detector

This paper introduces a power-aware behavioral modeling approach for analog components. A Verilog-A behavioral model, which considers the component´s current consumption, is created using circuit information obtained from transistor-level simulation. Therefore, the model features high accuracy with the benefit of low computational effort. The concept can be applied to any analog component and enables the simulation of complex analog systems. The approach is practically applied to the design of a phase-frequency detector, which determines important characteristics of a PLL.