Title :
Testing gate-to-channel shorts in BiCMOS logic gates
Author :
Chen, C.-J. ; Mourad, S.
Author_Institution :
Dept. of Electr. Eng., Santa Clara Univ., CA, USA
Abstract :
The effects of gate to channel breakdown on the operation of BiCMOS logic gates are described. Both the static and dynamic behaviors of the gates are examined. The results of a SPICE simulation are presented. They show that gate to channel breakdown cannot be modeled by a stuck-at fault. Iddq and delay testings are effective in detecting these defects. Test patterns for Iddq are given
Keywords :
BiCMOS integrated circuits; integrated circuit testing; integrated logic circuits; logic gates; logic testing; BiCMOS logic gates; SPICE simulation; delay testings; dynamic behaviour; gate-to-channel shorts; static behaviour; BiCMOS integrated circuits; CMOS logic circuits; CMOS technology; Circuit faults; Circuit testing; Electric breakdown; Inverters; Logic gates; Logic testing; Semiconductor device modeling;
Conference_Titel :
ASIC Conference and Exhibit, 1992., Proceedings of Fifth Annual IEEE International
Conference_Location :
Rochester, NY
Print_ISBN :
0-7803-0768-2
DOI :
10.1109/ASIC.1992.270221
