Title :
A 65nm 1Mb SRAM Macro with Dynamic Voltage Scaling in Dual Power Supply Scheme for Low Power SoCs
Author :
Fukano, G. ; Kushida, K. ; Tohata, A. ; Takeyama, Y. ; Imai, K. ; Suzuki, A. ; Yabe, T. ; Otsuka, N.
Author_Institution :
Toshiba Corp., Kawasaki
Abstract :
A power reduction technique is proposed for SRAM macros in which dual power supply scheme is combined with dynamic voltage scaling scheme. The test chip with 1Mb SRAM macro fabricated using 65nm CMOS process has demonstrated that the active power in low power mode is reduced by 25% compared to that of the conventional scheme. The leakage current at sleep mode is also decreased by three orders of magnitude compared to that of the conventional one.
Keywords :
CMOS memory circuits; SRAM chips; low-power electronics; system-on-chip; CMOS process; SRAM macro; dual power supply scheme; dynamic voltage scaling; leakage current; low power system-on-chip; power reduction technique; size 65 nm; sleep mode; storage capacity 1 Mbit; CMOS technology; Degradation; Driver circuits; Dynamic voltage scaling; Leakage current; Power dissipation; Power supplies; Random access memory; Stability; Testing;
Conference_Titel :
Non-Volatile Semiconductor Memory Workshop, 2008 and 2008 International Conference on Memory Technology and Design. NVSMW/ICMTD 2008. Joint
Conference_Location :
Opio
Print_ISBN :
978-1-4244-1546-5
Electronic_ISBN :
978-1-4244-1547-2
DOI :
10.1109/NVSMW.2008.34
