Automatic logic and timing model generation for cell based design

A proven methodology for generating and maintaining ASIC libraries automatically, and the software used in implementing this methodology are described. The models generated by this methodology are consistent in terms of functionality, naming, attributes and other characteristics. The models generated by each generator are considered correct by construction, once the operation of the generator is verified. Therefore, functional verification is reduced to a single task of verification of the generator, compared to the verification of each model generated through manual efforts