Title :
A pipeline FFT processor
Author :
Li, Weidong ; Wanhammar, Lars
Author_Institution :
Dept. of Electr. Eng., Linkoping Univ., Sweden
fDate :
6/21/1905 12:00:00 AM
Abstract :
We discuss the design and implementation of a high-speed, low power 1024-point pipeline FFT processor. Key features are flexible internal data length and a novel processing element. The FFT processor, which is implemented in a standard 0.35 μm CMOS process, is efficient in terms of power consumption and chip area
Keywords :
CMOS digital integrated circuits; digital signal processing chips; fast Fourier transforms; pipeline processing; CMOS; chip area; flexible internal data length; high-speed low power pipeline processor; pipeline fast Fourier transform processor; power consumption; CMOS process; Delay; Digital signal processing chips; Energy consumption; Fast Fourier transforms; Flexible printed circuits; Hardware; Pipelines; Speech processing; Throughput;
Conference_Titel :
Signal Processing Systems, 1999. SiPS 99. 1999 IEEE Workshop on
Conference_Location :
Taipei
Print_ISBN :
0-7803-5650-0
DOI :
10.1109/SIPS.1999.822372
