DocumentCode
1606933
Title
Improved modelling and characterization system for logic simulation
Author
Misheloff, Michael N.
Author_Institution
COMPASS Design Autom., San Jose, CA, USA
fYear
1992
Firstpage
331
Lastpage
334
Abstract
An accurate input ramp-dependent timing model and practical characterization system is described. Compared to current implementations, the system drastically reduces the number of circuit simulations required for cell library characterization. Errors of the model predictions for delay chains are typically less than 2%
Keywords
circuit analysis computing; logic CAD; cell library characterization; characterization system; circuit simulations; input ramp-dependent timing model; logic simulation; modelling; Circuit simulation; Delay; Design automation; Inverters; Logic design; Predictive models; Proposals; Semiconductor device modeling; Timing; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
ASIC Conference and Exhibit, 1992., Proceedings of Fifth Annual IEEE International
Conference_Location
Rochester, NY
Print_ISBN
0-7803-0768-2
Type
conf
DOI
10.1109/ASIC.1992.270225
Filename
270225
Link To Document