DocumentCode
1607063
Title
A Study of Sub-40nm FinFET BE-SONOS NAND Flash
Author
Hsu, Tzu-Hsuan ; Lue, Hang-Ting ; Peng, Wu-Chin ; Tsai, Cheng-Hung ; King, Ya-Chin ; Wang, Szu-Yu ; Wu, Ming-Tsung ; Hong, Shih-Ping ; Hsieh, Jung-Yu ; Yang, Ling-Wu ; Lian, Nan-Tzu ; Yang, Tahone ; Chen, Kuang-Chao ; Hsieh, Kuang-Yeu ; Liu, Rich ; Lu, Ch
Author_Institution
Emerging Central Lab. Ltd., Hsinchu
fYear
2008
Firstpage
115
Lastpage
116
Abstract
Sub-40nm body-tied FinFET BE-SONOS NAND Flash is studied extensively. BE-SONOS offers efficient hole tunneling erase and excellent data retention. When integrated into a FinFET structure, the inherent field enhancement (FE) effect around the fin tip provides very faster program/erase speed. However, the non-uniform injection around the fin also greatly complicates the operation of FinFET BE-SONOS. In this work, the switching mechanisms at the fin tip, sidewall and bottom corner are examined in detail, thus providing insights to optimize the FinFET geometry. For the first time, we demonstrate that the ISPP together with self-boosting program-inhibit methods provide excellent Vt distribution control for MLC application for a FinFET CT device.
Keywords
MOSFET; flash memories; tunnelling; FinFET BE-SONOS NAND flash; FinFET structure; data retention; hole tunneling erase; inherent field enhancement effect; nonuniform injection; Capacitors; Degradation; Electronic mail; Electrons; FinFETs; Geometry; Iron; Neck; Tunneling; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Non-Volatile Semiconductor Memory Workshop, 2008 and 2008 International Conference on Memory Technology and Design. NVSMW/ICMTD 2008. Joint
Conference_Location
Opio
Print_ISBN
978-1-4244-1546-5
Electronic_ISBN
978-1-4244-1547-2
Type
conf
DOI
10.1109/NVSMW.2008.39
Filename
4531839
Link To Document