DocumentCode
1607126
Title
A DSP architecture for 64 kbps motion video codec
Author
Murakami, Tokumichi ; Kamizawa, Koh ; Kameyama, Masatoshi ; Nakagawa, Shinichi
Author_Institution
Mitsubishi Electr. Corp., Tokyo, Japan
fYear
1988
Firstpage
227
Abstract
The authors describe an architectural study of a digital signal processor (DSP) well suited for video codec. This DSP consists of specified resources optimized for video signal processing, such as the instruction set, buses, data memories, execution unit, address generators, sequencer, and DMAC. The performance of the DSP is evaluated through several video coding sequences. The architecture of a multiprocessor configuration for video codec, which will allow flexible algorithm and variable picture format, is also examined.<>
Keywords
codecs; digital signal processing chips; video signals; 64 kbit/s; DMAC; DSP architecture; address generators; buses; coding sequences; data memories; digital signal processor; execution unit; flexible algorithm; instruction set; multiprocessor configuration; picture format; sequencer; video codec; video signal processing; Arithmetic; Convolution; Digital signal processing; Laboratories; Read-write memory; Signal processing algorithms; Vector quantization; Video codecs; Video coding; Video signal processing;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 1988., IEEE International Symposium on
Conference_Location
Espoo, Finland
Type
conf
DOI
10.1109/ISCAS.1988.14908
Filename
14908
Link To Document