A 0.6V, 0.17mW, 120% bandwidth double-gate double-balanced mixer in a 180 nm CMOS technology

In this paper, an ultra-low-power double-balanced mixer in a 180 nm CMOS technology is presented and demonstrated. An out-phase double-gate LO feeding technique is proposed to decrease the power consumption. Furthermore, body biasing is used to decrease the supply voltage. The measured maximum conversion gain is 11.9 dB and the 3 dB bandwidth is more than 120 %. The measured double sideband noise figure is 15.9 dB. The power consumption is as low as 0.17 mW with a supply voltage of 0.6 V. The chip has an outstanding FOM of 19.4. The results show significant improvements on low-voltage and low-power design. The occupied chip area including pads is 0.7 mm × 0.5 mm.